The following related patent applications, assigned to the same assignee hereof and filed on even date herewith in the names of the same inventors as the present application, disclose related subject matter, with the subject of each being incorporated by reference herein in its entirety:
Memory Module with Hierarchical Functionality, Ser. No. 09/775,477; High Precision Delay Measurement Circuit, Ser. No. 09/776,262; Single-Ended Sense Amplifier with Sample-and-Hold Reference, Ser. No. 09/776,220; Limited Switch Driver Circuit, Ser. No. 09/775,478 Fast Decoder with Asynchronous Reset with Row Redundancy; Ser. No. 09/775,476; Diffusion Replica Delay Circuit, Ser. No. 09/776,029; Sense Amplifier with Offset Cancellation and Charge-Share Limited Swing Drivers, Ser. No. 09/775,475; Memory Architecture with Single-Port Cell and Dual-Port (Read and Write) Functionality, Ser. No. 09/775,701; Memory Redundancy Implementation, Ser. No. 09/776,263; and; A Circuit Technique for High Speed Low Power Data Transfer Bus, Ser. No. 09/776,028.
1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like.
The present invention satisfies the above needs by providing a sense amplifier adapted to sense an input signal on corresponding global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet a residual offset signal value. The offset equalization network substantially eliminates the residual offset signal value. The sense amplifier also can include, alone or in combination with the aforementioned offset networks, an isolation circuit isolates the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit can be employed, which shares charge between the corresponding global bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the corresponding bit lines. The sense amplifier can employ an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor. Furthermore, the charge-sharing circuit includes a precharging circuit, precharging the corresponding bitlines, and a charge reservoir, selectively sourcing and sinking charge, being responsive when the sense amplifier is used. The sense amplifier can be a latch-type differential sense amplifier.